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communication semiconductors CMX909B data bulletin gmsk packet data modem mobitex tm is a trademark of telia ab, sweden 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. features and applications ? gmsk modulation/demodulation ? rx or tx up to 38.4kbits/sec ? full and short data packet framing ? mobitex tm compatible including r14n short block frames ? envelope/end of packet detector for ?continuously keyed carrier? systems ? on-chip packet detection ? parallel host processor interface ? low power 3.0v/5.0v operation ? flexible operating and powersave modes data a n d control bus rf radio discriminator modulator system application processing host c gmsk modem CMX909B gmsk modulator frame sync. and data detection scramble data interleave data fec & crc encoding fec & crc decoding gmsk demodulator add frame header descramble data deinterleave data data buffer analog tx analog rx the CMX909B is a half-duplex gaussian minimum shift keyed (gmsk) bt=0.3 modem data pump with on- chip packet data handling. gmsk modulation optimizes the data throughput for a given bandwidth rf channel and the on-chip packet data handling relieves the host c of regular processing tasks, such as maintaining bit and frame synchronization, block formatting, crc and fec error processing, data interleaving and scrambling. the demodulator uses decision feedback equalization techniques to reduce the channel distortion effects and enhance the receiver performance without the computational overhead of maximum likelihood (viterbi) estimation methods. the CMX909B is pin, function and software backwards compatible with the fx909a and mx909a modems and also uses the same external components. it offers improved performance, higher data rates, lower voltage operation, support for the recent r14n extension to mobitex for short block frames, and an envelope/end of packet detector to facilitate frame start detection in ?continuously keyed carrier? systems. the CMX909B also offers 2-strength xtal driver circuitry ? for wider choice of xtals, optional zero-error or one-error frame sync. detection, multiple powersave options ? for intelligent power management, and availability in small 24-pin tssop and ssop package options. the CMX909B is ideally suited to wireless data applications such as mobitex terminals, wireless telemetry, license-free radio data and ism band radio schemes.
gmsk packet data modem 2 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. contents section page 1. block diagram ............................................................................................................... 4 2. signal list .................................................................................................................... .. 5 3. external components ................................................................................................... 6 4. general description ...................................................................................................... 7 4.1 description of blocks ......................................................................................................... 7 4.1.1 data bus buffers............................................................................................................... ...... 7 4.1.2 address and r/w decode ...................................................................................................... 7 4.1.3 status and data quality registers.......................................................................................... 7 4.1.4 command, mode and control registers ................................................................................ 7 4.1.5 data buffer.................................................................................................................... .......... 7 4.1.6 crc generator/checker ........................................................................................................ 7 4.1.7 fec generator/checker ......................................................................................................... 7 4.1.8 interleave/de-interleave buffer ............................................................................................... 7 4.1.9 frame sync detect .............................................................................................................. ... 8 4.1.10 rx i/p amp..................................................................................................................... ......... 8 4.1.11 tx/rx low pass filter .......................................................................................................... ... 8 4.1.12 tx output buffer............................................................................................................... ....... 8 4.1.13 rx level/clock extraction...................................................................................................... .9 4.1.14 clock oscillator and dividers.................................................................................................. 9 4.1.15 scramble/de-scramble ........................................................................................................... 9 4.2 modem - c interaction ................................................................................................... 10 4.3 data formats ................................................................................................................... 11 4.3.1 general purpose formats .................................................................................................... 11 4.3.1.1 mobitex frame structure ................................................................................................ 11 4.4 the programmer?s view................................................................................................... 12 4.4.1 data buffer.................................................................................................................... ........ 12 4.4.2 command register ............................................................................................................... 13 4.4.2.1 command register b7: aqbc - acquire bit clock ........................................................ 13 4.4.2.2 command register b6: aqlev - acquire receive signal levels ................................. 13 4.4.2.3 command register b5: - eop end of packet detector ................................................ 14 4.4.2.4 command register b4: - env envelope detector........................................................ 14 4.4.2.5 command register b3, b2, b1, b0: task - task ......................................................... 15 4.4.3 control register ............................................................................................................... ..... 22 4.4.3.1 control register b7, b6: ckdiv - clock division ratio ................................................. 22 4.4.3.2 b5: lo hi/ - xtal range selection ................................................................................. 22 4.4.3.3 control register b4: dara - data rate and mode register b0 - hibw ....................... 22 4.4.3.4 control register b3, b2: levres - level measurement response time .................... 23 4.4.3.5 control register b1, b0: pllbw ................................................................................... 23
gmsk packet data modem 3 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.4 mode register.................................................................................................................. ..... 23 4.4.4.1 mode register b7: en irq - irq output enable ........................................................ 23 4.4.4.2 mode register b6: invbit - invert bits.......................................................................... 24 4.4.4.3 mode register b5: r x tx/ - tx/rx mode...................................................................... 24 4.4.4.4 mode register b4: scren - scramble enable ............................................................. 24 4.4.4.5 mode register b3: psave - powersave........................................................................ 24 4.4.4.6 mode register b2: dqen - data quality irq enable ................................................... 24 4.4.4.7 mode register b1: hixtl - high xtal drive ................................................................... 24 4.4.4.8 mode register b0: hibw - high filter bandwidth.......................................................... 24 4.4.5 status register ................................................................................................................ ..... 25 4.4.5.1 status register b7: irq - interrupt request .................................................................. 25 4.4.5.2 status register b6: bfree - data buffer free ............................................................. 25 4.4.5.3 status register b5: ibempty - interleave buffer empty............................................... 25 4.4.5.4 status register b4: dibovf - de-interleave buffer overflow ....................................... 26 4.4.5.5 status register b3: crcfec - crc or fec error ........................................................ 26 4.4.5.6 status register b2: dqrdy - data quality reading ready ......................................... 26 4.4.5.7 status register b1: ba mo/ - mobile or base bit sync received ................................ 26 4.4.5.8 status register b0: eop/env - end of packet/envelope detect .................................. 26 4.4.6 data quality register.......................................................................................................... .. 27 4.5 crc, fec, interleaving and scrambling information: ...................................................... 28 4.5.1 crc ............................................................................................................................ .......... 28 4.5.2 fec............................................................................................................................ ........... 28 4.5.3 interleaving ................................................................................................................... ........ 29 4.5.4 scrambling ..................................................................................................................... ....... 30 5. application notes........................................................................................................ 30 5.1 transmit frame example................................................................................................. 30 5.2 receive frame example.................................................................................................. 32 5.3 clock extraction and level measurement systems.......................................................... 34 5.4 ac coupling.................................................................................................................... .36 5.5 radio performance .......................................................................................................... 37 6. performance specification ......................................................................................... 38 6.1 electrical performance..................................................................................................... 38 6.1.1 absolute maximum ratings .................................................................................................. 38 6.1.2 operating limits............................................................................................................... ..... 38 6.1.3 operating characteristics ..................................................................................................... 3 9 6.1.4 timing diagrams................................................................................................................ ... 40 6.2 packaging...................................................................................................................... .. 42 mx-com, inc. reserves the right to change specifications at any time and without notice.
gmsk packet data modem 4 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 1. block diagram v ss v bias xtal / clock txout rxin rx input amp tx output buffer doc1 doc2 d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 8 tx tx bits rx bits tx rx tx rx rx v bias contr oller interf ace data bus buffers address and r/w decode crc generator/ checker frame sync detect rx level/clock extraction fec generator/ checker interleave/ de-interleave scramble/ de-scramble control register mode register command register data buffer status register data quality register low pass filter clock oscillator and dividers rxampout v dd xtal wr rd cs irq v dd v bias figure 1: block diagram
gmsk packet data modem 5 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 2. signal list package e2/d5/p4 signal description pin no. name type 1 irq output a ?wire-orable? output for connection to the host c's interrupt request input. this output has a low impedance pull down to v ss when active and is high impedance when inactive. 2 d7 bi-directional 3 d6 bi-directional 4 d5 bi-directional 5 d4 bi-directional 6 d3 bi-directional 7 d2 bi-directional 8 d1 bi-directional 9 d0 bi-directional 8-bit bi-directional 3-state c interface data lines. 10 rd input read. an active low logic level input used to control the reading of data from the modem into the host c. 11 wr input write. an active low logic level input used to control the writing of data into the modem from the host c. 12 v ss power the negative supply rail (ground). 13 cs input chip select. an active low logic level input to the modem, used to enable a data read or write operation. 14 a0 input 15 a1 input two logic level modem register select inputs. 16 xtal output the output of the on-chip oscillator. 17 xtal/clock input the input to the on-chip oscillator, for external xtal circuit or clock. 18 doc 2 output 19 doc 1 output connections to the rx level measurement circuitry. a capacitor should be connected from each pin to v ss . 20 txout output the tx signal output from the modem. 21 v bias output a bias line for the internal circuitry, held at v dd /2. this pin must be decoupled to v ss by a capacitor mounted close to the device pins. 22 rxin input the input to the rx input amplifier. 23 rxfb output the output of the rx input amplifier and the input to the rx filter. 24 v dd power the positive supply rail. levels and voltages are dependent upon this supply. this pin should be decoupled to v ss by a capacitor. note: to achieve good noise performance, v dd and v bias decoupling and protection of the receive path from extraneous in-band signals are very important. it is recommended that the printed circuit board is laid out with a ground plane in the CMX909B area to provide a low impedance connection between the v ss pin and the v dd and v bias decoupling capacitors. it is also important to achieve a low impedance connection between the xtal capacitors (c3 and c4) and the ground plane.
gmsk packet data modem 6 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 3. external components doc1 doc2 v dd v dd v ss v bi a s rxin gmskin gmskout rxampout r2 r4 r1 contr oller interf ace CMX909B txout c7 c5 c3 c4 r3 x1 c6 c1 c2 d7 d6 d5 d4 d3 d2 d1 d0 a0 a1 a1 a0 xtal/clock xtal/clock 1 2 3 4 5 6 8 9 10 11 12 13 14 7 24 23 22 21 20 19 18 17 17 16 16 15 irq xtal xtal rd wr cs cs figure 2: recommended external components r1 note 1 20% c3 note 3, 4 20% r2 100k ? 10% c4 note 3, 4 20% r3 1m ? * 20% c5 note 2 10% r4 note 2 5% c6 20% c1 0.1 f 20% c7 20% c2 0.1 f 20% x1 note 3, 4 notes: 1. see section 4.1.10 2. see section 4.1.12 3. see section 4.4.3* 4. see section 4.1.14 5. c6 and c7 values should satisfy the following: c (in farads) x data rate (bits/second) = 120 x 10 -6 e.g. data rate (kbits/sec) c6/c7 (nf) data rate (kbits/sec) c6/c7 (nf) 4.0 30 16.0 6.8 4.8 22 19.2 6.8 8.0 15 32.0 3.9 9.6 12 38.4 3.3
gmsk packet data modem 7 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4. general description this product has been designed to be compliant with the appropriate sections of the "mobitex interface specification" including short block frame formatting for the extended battery saving protocol. references to ?data blocks? in this document apply to both the normal (18 byte) data block and the smaller (4 byte) short data block. 4.1 description of blocks 4.1.1 data bus buffers 8 bi-directional 3-state logic level buffers between the modem?s internal registers and the host c's data bus lines. 4.1.2 address and r/w decode this block controls the transfer of data bytes between the c and the modem's internal registers, according to the state of the write and read enable inputs ( wr and rd ), the chip select input ( cs ) and the register address inputs a0 and a1. the data bus buffers, address and r/w decode blocks provide a byte-wide parallel c interface, which can be memory-mapped, as shown in figure 3. address bus c modem wr rd cs rd address decode circuit data bus irq v dd d0:7 a0:1 wr irq pull up resistor d0:7 irq a2:7 a0:1 figure 3: typical modem c connections 4.1.3 status and data quality registers 8-bit registers which the c can read to determine the status of the modem and the received data quality. 4.1.4 command, mode and control registers the values written by the c to these 8-bit registers control the operation of the modem. 4.1.5 data buffer an 18-byte buffer used to hold receive or transmit data to or from the c. 4.1.6 crc generator/checker a circuit which generates (in transmit mode) or checks (in receive mode) the cyclic redundancy checksum bits, which are included in transmitted mobitex data blocks so that the receive modem can detect transmission errors. 4.1.7 fec generator/checker in transmit mode this circuit calculates and adds the forward error correction (4 bits) to each byte presented to it. in receive mode the fec information is used to correct most transmission errors that have occurred in mobitex data blocks or in the frame head control bytes. 4.1.8 interleave/de-interleave buffer this circuit interleaves data bits within a data block before transmission and de-interleaves the received data block so that the fec system is best able to handle short noise bursts or signal fades.
gmsk packet data modem 8 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.1.9 frame sync detect this circuit, which is only active in receive mode, is used to look for the user specified 16-bit frame synchronization pattern which is transmitted to mark the start of every frame. 4.1.10 rx i/p amp this amplifier allows the received signal input to the modem to be set to the optimum level by suitable selection of the external components r1 and r2. the value of r1 should be calculated to give 0.2 x v dd peak to peak at the rxfb pin for a received ?...11110000...? sequence. a capacitor may be fitted if ac coupling of the received signal is desired (see section 5.4), otherwise the dc level of the received signal should be adjusted so that the signal at the modem's rxfb pin is centered around v bias (v dd /2). 4.1.11 tx/rx low pass filter this filter, which is used in both transmit and receive modes, is a low pass transitional gaussian filter having a loss of 3db at 0.3 times the selected bit rate (bt = 0.3). see figure 4. in transmit mode, the bits are passed through this filter to eliminate the high frequency components which would otherwise cause interference into adjacent radio channels. in receive mode this filter is used with an increased bt factor (0.56) to reject hf noise, so that the signal is suitable for extraction of the received data. 4.1.12 tx output buffer this is a unity gain amplifier used in transmit mode to buffer the output of the tx low pass filter. in receive mode, the input of this buffer is connected to v bias . when changing from rx to tx mode the input to this buffer will be connected to v bias for 2 bit periods to prevent unwanted signals, from the low pass filter, at the output. when the modem is set to power save mode, the buffer is turned off and the txout pin connected to v bias via a high value resistance. when exiting from power save mode the tx output is only reconnected to the buffer after 2 bit periods, to prevent unwanted signals, from the low pass filter, at the output. note: the rc low pass filter formed by the external components r4 and c5 between the tx output buffer and the input to the radio's frequency modulator forms an important part of the transmit signal filtering. these components may form part of any dc level-shifting and gain adjustment circuitry. the ground connection to the capacitor c5 should be positioned to give maximum attenuation of high frequency noise into the modulator. r4 and c5 should be chosen so that the product of the resistance of r4 (in ohms) and capacitance of c5 (in farads) is 0.34/bit rate (bit rate in bits per second). r4 should be not less than 47k ? and the value used for the external capacitor should take into account parasitic capacitance. suitable values being: r4 c5 8000bps 100k ? 430pf 4800bps 100k ? 710pf the signal at the txout pin is centered around v bias and is approx 0.2 x v dd peak to peak, going positive for a logic ?1? and negative for a logic ?0?, if the modem is not inverting the tx data. a capacitor may be fitted if ac coupling of the input to the frequency modulator is desired, see section 5.4. the ?eye? diagram of the transmitted signal (after the external r4/c5 network) is shown in figure 5.
gmsk packet data modem 9 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 gain (db) frequency/data rate figure 4: typical tx filter frequency response (after the external rc filter) 0 12 figure 5: transmitted signal eye diagram (after the external rc filter) 4.1.13 rx level/clock extraction these circuits, which operate only in receive mode, extract a bit rate clock from the received signal and measure the received signal amplitude and dc offset. this information is then used to extract the received bits and also to provide an input to the received data quality measuring circuit. the external capacitors c6 and c7 form part of the received signal level measuring circuit. 4.1.14 clock oscillator and dividers this circuit derives the transmit bit rate (and the nominal receive bit rate) by frequency division of a reference frequency which may be generated by the on-chip xtal oscillator or applied from an external source. note: if the on-chip xtal oscillator is to be used, then the external components x1, c3, c4 and r3 are required. if an external clock source is to be used, then it should be connected to the xtal/clock input pin, the xtal pin should be left unconnected, and x1, c3, c4 and r3 not fitted. 4.1.15 scramble/de-scramble this block may be used to scramble/de-scramble the transmitted/received data blocks. it does this by modulating the data with a 511-bit pseudorandom sequence, as described in section 4.5.4. scrambling smoothes the transmitted spectrum, especially when repetitive sequences are to be transmitted.
gmsk packet data modem 10 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.2 modem - c interaction in general, data is transmitted over air in the form of messages, or ?frames?, consisting of a ?frame head? optionally followed by one or more formatted data blocks. the frame head includes a frame synchronization pattern designed to allow the receiving modem to identify the start of a frame. the following data blocks are constructed from the ?raw? data using a combination of crc (cyclic redundancy checksum) generation, forward error correction coding, interleaving and scrambling. details of the message formats handled by this modem are given in section 4.3. to reduce the processing load on the host c, this modem has been designed to perform as much as possible of the computationally intensive work involved in frame formatting and de-formatting and (when in receive mode) in searching for and synchronizing onto the frame head. in normal operation the modem will only require servicing by the c once per received or transmitted data block. thus, to transmit a block, the host c has only to load the unformatted (raw) binary data into the modem's data buffer then instruct the modem to format and transmit that data. the modem will then calculate and add the crc bits as required, encode the result with forward error correction coding, interleave then scramble the bits before transmission. in receive mode, the modem can be instructed to assemble a block?s worth of received bits, de-scramble and de-interleave the bits, check and correct them (using the fec coding) and check the resulting crc before placing the received binary data into the data buffer for the c to read. the modem can also handle the transmission and reception of unformatted data, to allow the transmission of special bit and frame synchronization sequences or test patterns.
gmsk packet data modem 11 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.3 data formats 4.3.1 general purpose formats in a proprietary system the user may employ the data elements provided by this device to construct a custom, over-air data structure. for example, 16 bits of bit sync + 2 bytes of frame sync + 4 bytes of receiver and sender address + n data blocks would be sent as: tqb (bit and frame sync) + tqb (addresses) + (n x tdb) + tsb and received as: sfs + rsb + rsb + rsb + rsb + (n x rdb) note: it is important to have established frame synchronization before receiving data to enable the receiving device to decode synchronously. also the user may add, by way of algorithms performed on the controlling device, additional data correction with the bytes in the data block task. 4.3.1.1 mobitex frame structure the mobitex format for transmitted data is in the form of a frame head immediately followed by either 1 short data block or a number of data blocks (0 to 32). the frame head consists of 7 bytes: 2 bytes of bit sync: 1100110011001100 from base, 0011001100110011 from mobile bits are transmitted from left to right 2 bytes of frame sync: system specific. 2 bytes of control data. 1 byte of fec code, 4 bits for each of the control bytes: bits 7-4 (leftmost) operate on the first control byte. bits 3-0 (rightmost) operate on the second control byte. each byte in the frame head is transmitted bit 7 (msb) first to bit 0 (lsb) last. the data blocks consist of: 18 bytes of data (data block) or 4 bytes of data (short data block). 2 bytes of crc calculated from the data bytes. 4 bits of fec code for each of the data and crc bytes the resulting data block bits are interleaved and scrambled before transmission. figure 6 shows how the over air signal is built up from frame sync and bit sync patterns, control bytes and data blocks. the binary data transferred between the modem and the host c is that shown enclosed by the thick dashed rectangles near the top of the diagram.
gmsk packet data modem 12 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. interleaving / de-interleaving scramble / descramble 7654321 0 crc (2 bytes) loaded first loaded last 4 5 6 7 8 9 0 1 2 3 18 19 14 15 16 17 10 11 12 13 fec lsb msb 321 0 76543210 frame head msb lsb fec2 fec1 byte loaded first loaded last 1 2 4 3 5 6 data block db 0 db n db 1 db 2 db 3 db 4 frame sync 16 16 8 frame head 16 bits ctrl bytes bit sync fec data blocks data blocks (0 to 32) frame over - air signal 0 byte data (18 bytes) bit sync 1 bit sync 2 frame sync 1 frame sync 2 control byte 1 control byte 2 figure 6: mobitex over air signal format 4.4 the programmer?s view the modem appears to the programmer as 4 write only 8-bit registers shadowed by 3 read only registers, individual registers being selected by the a0 and a1 chip inputs: a1 a0 write to modem read from modem 0 0 data buffer data buffer 0 1 command register status register 1 0 control register data quality register 1 1 mode register not used 4.4.1 data buffer this is an 18-byte read/write buffer which is used to transfer data (as opposed to command, status, mode, data quality and control information) between the modem and the host c. it appears to the c as a single 8-bit register; the modem ensuring that sequential c reads or writes to the buffer are routed to the correct locations within the buffer. the c should only access this buffer when the status register bfree (buffer free) bit is ?1?. the buffer should only be written to while in tx mode and read from while in rx mode (except when loading frame sync detection bytes while in rx mode).
gmsk packet data modem 13 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.2 command register writing to this register tells the modem to perform a specific action or actions, depending on the setting of the task, aqlev and aqbc bits. the env and eop bits are used to indicate the presence of signals in the receive path. 76543210 command register aqbc aqlev task eop env when it has no action to perform (but is not ?powersaved?), the modem will be in an ?idle? state. if the modem is in transmit mode the input to the tx filter will be connected to v bias . in receive mode the modem will continue to measure the received data quality and extract bits from the received signal, supplying them to the de-interleave buffer, but will otherwise ignore the received data. 4.4.2.1 command register b7: aqbc - acquire bit clock this bit has no effect in transmit mode. in receive mode, whenever a byte with the aqbc bit set to ?1? is written to the command register, and task is not set to reset, it initiates an automatic sequence designed to achieve bit timing synchronization with the received signal as quickly as possible. this involves setting the phase locked loop of the received bit timing extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing synchronization is achieved, until it reaches the 'normal' value set by the pllbw bits of the control register. setting this bit to ?0? (or changing it from ?1? to ?0?) has no effect, note however, that the acquisition sequence will be re-started every time that a byte written to the command register has the aqbc bit set to ?1?. the aqbc bit will normally be set up to 12 bits before an sfs (search for frame sync) or sfh (search for frame head) task, however it may also be used independently to re-establish clock synchronization quickly after a long fade. alternatively, a sfs or sfh task may be written to the command register with the aqbc bit ?0? if it is known that clock synchronization does not need to be re-established. more details of the bit clock acquisition sequence are given in section 5.3. 4.4.2.2 command register b6: aqlev - acquire receive signal levels this bit has no effect in transmit mode. in receive mode, whenever a byte with the aqlev bit set to ?1? is written to the command register and task is not set to reset, it initiates an automatic sequence designed to measure the amplitude and dc offset of the received signal as rapidly as possible. this sequence involves setting the measurement circuits to respond quickly at first, then gradually increasing their response time, hence improving the measurement accuracy, until the ?normal? value set by the levres bits of the control register is reached. setting this bit to ?0? (or changing it from ?1? to ?0?) has no effect, note however, that the acquisition sequence will be re-started every time that a byte written to the command register has the aqlev bit set to ?1?. the aqlev bit will normally be set up to 12 bits before an sfs (search for frame sync) or sfh (search for frame head) task is initiated, however it may also be used independently to re-establish signal levels quickly after a long fade. alternatively, a sfs or sfh task may be written to the command register with the aqlev bit at ?0? if it is known that there is no need to re-establish the received signal levels. more details of the level measurement acquisition sequence are given in section 5.3. the error rate is highest immediately after a aqbc and aqlev sequence is triggered and rapidly reduces to its static value soon after. these erroneous bits could incorrectly trigger the frame sync detection circuits and so it is suggested that a sfh or sfs task is set 12 bits after setting either of the aqlev or aqbc sequences.
gmsk packet data modem 14 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.2.3 command register b5: - eop end of packet detector this bit has no effect in transmit mode. in receive mode, whenever this bit is set to ?1?, a circuit monitors the receive wave form. if the received signal remains close to the center of the received data levels (as stored on the doc capacitors) for more than approximately 3 bit times then the logic output will be set high and bit ?0? of the status register will be set according to the table below. if the input signal level goes toward either of the doc capacitor values the logic output will be immediately set low. note: if this bit is set when a data signal is not being received and the doc capacitors have discharged or if there are high levels of noise, its output will be unreliable. it should be used in conjunction with bit 4 of the command register. 4.4.2.4 command register b4: - env envelope detector this bit has no effect in transmit mode. in receive mode, whenever this bit is set to ?1?, a circuit monitors the doc voltage levels. if the doc voltages are more than 4% of v dd apart (0.2v when v dd = 5.0v) then the logic output will be set high and bit ?0? of the status register will be set according to the table below. n ote: if this bit is set the env output will also be triggered when receiving high levels of noise or other in- band signals. b5 (eop) b4 (env) status register b0 (state set to output of): irq triggered on: (if enabled) 0 0 0 - 0 1 env detector 0 1 1 0 eop detector 0 1 1 1 (env) and ( eop ) 0 1 or 1 0 if both b4 and b5 are set the status register will be set whenever: (envelope detector output = high) and (end of packet output = low). the status register b0 will then be high during the most likely time that a packet is being received. in this mode the irq bit will be set on both edges, thus indicating the likely time of the start and end of packets. if either b5 or b4 are set high then b0 and b1 of the data quality register will directly follow the outputs of the env and eop circuits respectively. if b5 and b4 are set low the data quality register bits b0 and b1 will still indicate the output of the env and the eop circuits but the irq bit will not be set in this case. the following actions will restore the data quality bits b0 and b1 to indicating the data quality value: issuing a reset command, setting r x tx / bit = ?1? or by entering power save mode. note: because the least significant bits of the data quality register are used there will be no noticeable loss of accuracy in the dq reading and in this case the host processor can either ignore or mask out the 2 least significant bits when reading the dq value. note: the setting of the aqlev and levres bits is important to the correct operation of these circuits. see section 5.3 for more details.
gmsk packet data modem 15 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.2.5 command register b3, b2, b1, b0: task - task operations such as transmitting a data block are treated by the modem as ?tasks? and are initiated when the c writes a byte to the command register with the task bits set to one of the data handling commands (marked bold in the table below). mobitex modem tasks: b3 b2 b1 b0 receive mode transmit mode 0 0 0 0 null null 0 0 0 1 sfh search for frame head t7h transmit 7 byte frame head 0 0 1 0 r3h read 3 byte frame head reserved 0 0 1 1 rdb read data block tdb transmit data block 0 1 0 0 sfs search for frame sync tqb transmit 4 bytes 0 1 0 1 rsb read single byte tsb transmit single byte 0 1 1 0 lfsb load frame sync bytes tso transmit scrambler output 0 1 1 1 reset cancel any current action reset cancel any current action 1 0 0 1 sfhz sfh with zero errors reserved 1 0 1 1 rsd read short data block tsd transmit short data block 1 1 0 0 sfsz sfs with zero errors reserved 1 1 1 0 psbias turn off bias during power save 1 1 1 1 psbixt turn off bias and xtal during power save note: all other bit patterns are reserved. bold text indicates a ?data handling command? the c should not write a data handling command to the command register or write to or read from the data buffer when the bfree (buffer free) bit of the status register is ?0?. different tasks apply in receive and transmit modes. when the modem is in transmit mode, all data handling commands other than tso instruct the modem to transmit data from the data buffer, formatting it as required. for these tasks the c should wait until the bfree (buffer free) bit of the status register is ?1?, before writing the data to the data buffer, then it should write the desired task to the command register. if more than 1 byte needs to be written to the data buffer, byte number 0 of the block should be written first. once the byte containing the desired task has been written to the command register, the modem will: set the bfree (buffer free) bit of the status register to ?0?. take the data from the data buffer as quickly as it can - transferring it to the interleave buffer for eventual transmission. this operation will start immediately if the modem is ?idle? (i.e. not transmitting data from a previous task), otherwise it will be delayed until there is sufficient room in the interleave buffer. once all of the data has been transferred from the data buffer the modem will set the bfree and irq bits of the status register to ?1?, (causing the chip irq output to go low if the en irq bit of the mode register has been set to ?1?) to tell the c that it may write new data and the next task to the modem. in this way the c can write a task and the associated data to the modem while the modem is still transmitting the data from the previous task. see figure 7. when the modem is in receive mode, the c should wait until the bfree bit of the status register is ?1?, then write the desired task to the command register.
gmsk packet data modem 16 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. once the byte containing the desired task has been written to the command register, the modem will: set the bfree bit of the status register to ?0?. wait until enough received bits are in the de-interleave buffer. decode them as needed, and transfer any resulting data to the data buffer. then the modem will set the bfree and irq bits of the status register to ?1?, (causing the irq output to go low if the en irq bit of the mode register has been set to ?1?) to tell the c that it may read from the data buffer and write the next task to the modem. if more than 1 byte is contained in the data buffer, byte number ?0? of the data will be read first. in this way the c can read data and write a new task to the modem while the received bits needed for this new task are being stored in the de-interleave buffer. see figure 8. the above is not true for loading the frame sync detection bytes (lfsb): the bytes to be compared with the incoming data must be loaded prior to the task bits being written. detailed timings for the various tasks are given in figure 9 and figure 10. data from c to data buffer bfree bit of status register irq bit of status register irq irq output ( en = '1') txout signal task 1 data task 2 data task 1 from task 1 from task 2 task 2 task from c to command register figure 7: the transmit process data from data buffer to c bfree bit of status register rxin signal irq bit of status register irq irq outpu ( en = '1') task 1 data task 1 task 2 for task 1 for task 2 task from c to command register figure 8: the receive process
gmsk packet data modem 17 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.2.5.1 null - no effect this task is provided so that a aqbc or aqlev command can be initiated without loading a new task. 4.4.2.5.2 sfh - search for frame head causes the modem to search the received signal for a frame head. the frame head will consist of a 16-bit frame sync followed by control data (see figure 6- mobitex over air signal). the search will continue until a frame head has been found, or until the reset task is loaded. the search is carried out by first attempting to match the incoming bits against the previously programmed (task lfsb) 16-bit frame sync pattern (allowing up to any one bit (of 16) in error). when a match has been found, the modem will read the next 3 received bytes as frame head bytes, these bytes will be checked, and corrected if necessary, using the fec bits. the two frame head data bytes are then placed into the data buffer. the bfree and irq bits of the status register will then be set to a logic ?1? to indicate that the c may read the 2 frame head data bytes from the data buffer and write the next task to the command register. if the fec indicates uncorrectable errors the modem will set the crcfec bit in the status register to a logic ?1?. the ba mo/ (mobile or base) in the status register will be set according to the polarity of the 3 bits preceding the frame sync pattern. 4.4.2.5.3 r3h - read 3-byte frame head this task, which would normally follow an sfs task, will place the next 3 bytes directly into the data buffer. it also causes the modem to check the 3 bytes as frame head control data bytes and will set the crcfec bit to a logic ?1? (high) only if the fec bits indicate uncorrectable errors. note: this task will not correct any errors and, due to the mobitex fec specification, will not detect all possible uncorrectable error patterns the bfree and irq bits of the status register will be set to ?1? when the task is complete to indicate that the c may read the data from the data buffer and write the next task to the modem's command register. the crcfec bit in the status register will be set according to the validity of the received fec bits. 4.4.2.5.4 rdb - read data block this task causes the modem to read the next 240 bits as a mobitex data block. it will de-scramble and de-interleave the bits, fec correct and crc check the resulting 18 data bytes and place them into the data buffer, setting the bfree and irq bits of the status register to ?1? when the task is complete to indicate that the c may read the data from the data buffer and write the next task to the modem?s command register. the crcfec bit will be set according to the outcome of the crc check. note: in receive mode the crc checksum circuits are initialized on completion of any task other than null. 4.4.2.5.5 sfs - search for frame sync this task, which is intended for special test and channel monitoring purposes, performs the first part only of a sfh task. it causes the modem to search the received signal for a 16-bit sequence which matches the frame synchronization pattern with up to any 1 bit in error. when a match is found the modem will set the bfree and irq bits of the status register to ?1? and update the ba mo/ bit. the c may then write the next task to the command register. 4.4.2.5.6 rsb - read single byte this task causes the modem to read the next 8 bits and translate them directly (without de-interleaving or fec) to an 8-bit byte which is placed into the data buffer (b7 will represent the earliest bit received). the bfree and irq bits of the status register will then be set to ?1? to indicate that the c may read the data byte from the data buffer and write the next task to the command register. this task is intended for special tests and channel monitoring - perhaps preceded by an sfs task.
gmsk packet data modem 18 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.2.5.7 lfsb - load frame sync bytes this task takes 2 bytes from the data buffer and updates the frame sync detect bytes. the msb of byte ?0? is compared to the first bit of a received frame sync pattern and the lsb of byte ?1? is compared to the last bit of a received frame sync pattern. this task does not enable frame sync detection. unlike other rx tasks, the data buffer must be loaded before the task is issued and the task must only be issued ?between? received messages, i.e. before the first task for receiving a message and after the last data is read out of the data buffer. once the modem has read the frame sync bytes from the data buffer, the bfree and irq bits of the status register will be set to ?1?, indicating to the c that it may write the next task to the modem. 4.4.2.5.8 sfhz - search for frame head with zero errors this performs the same task as sfh task but allowing no bits to be in error over the 16-bit frame sync pattern. 4.4.2.5.9 rsd - read short data block this task causes the modem to read the next 72 bits as a mobitex short data block. it will de-scramble and de-interleave the bits, fec correct and crc check the resulting 4 data bytes and place them into the data buffer, setting the bfree and irq bits of the status register to ?1? when the task is complete to indicate that the c may read the data from the data buffer and write the next task to the modem?s command register. the crcfec bit will be set according to the outcome of the crc check. note: in receive mode the crc checksum circuits are initialized on completion of any task other than null. 4.4.2.5.10 sfsz - search for frame sync with zero errors this performs the same task as sfs task but allowing no bits to be in error over the 16-bit frame sync pattern. 4.4.2.5.11 t7h - transmit 7-byte frame head this task takes 6 bytes of data from the data buffer, calculates and appends 8 bits of fec from bytes ?4? and ?5? then transmits the result as a complete mobitex frame head. bytes ?0? and ?1? form the bit sync pattern, bytes ?2? and ?3? form the frame sync pattern and bytes ?4? and ?5? are the frame head control bytes. bit 7 of byte ?0? of the data buffer is sent first, bit 0 of the fec byte last. once the modem has read the data bytes from the data buffer, the bfree and irq bits of the status register will be set to ?1?, indicating to the c that it may write the next task and its data to the modem. 4.4.2.5.12 tqb - transmit 4 bytes this task takes 4 bytes of data from the data buffer and transmits them, bit 7 first. once the modem has read the data bytes from the data buffer, the bfree and irq bits of the status register will be set to ?1?, indicating to the c that it may write the next task and its data to the modem. 4.4.2.5.13 tdb - transmit data block this task takes 18 bytes of data from the data buffer, calculates and applies a 16-bit crc and forms the fec for the 18 data bytes and the crc. this data is then interleaved and passed through the scrambler, if enabled, before being transmitted as a mobitex data block. once the modem has read the data bytes from the data buffer, the bfree and irq bits of the status register will be set to ?1?, indicating to the c that it may write the next task and its data to the modem. note: in transmit mode the crc checksum circuit is initialized on completion of any task other than null. 4.4.2.5.14 tsb - transmit single byte this task takes a byte from the data buffer and transmits the 8 bits, bit 7 first. once the modem has read the data byte from the data buffer, the bfree and irq bits of the status register will be set to ?1?, indicating to the c that it may write the next task and its data to the modem. 4.4.2.5.15 tso - transmit scrambler output this task, intended for channel set-up, enables the scrambler and transmits its output. when the modem has started the task the status register bits will not be changed and hence an irq will not be raised. the c may write the next task and its data to the modem at any time and the scrambler output will stop when the new task has produced its first data.
gmsk packet data modem 19 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.2.5.16 tsd - transmit short data block this task takes 4 bytes of data from the data buffer, calculates and applies a 16-bit crc and forms the fec for the 4 data bytes and the crc. this data is then interleaved and passed through the scrambler, if enabled, before being transmitted as a mobitex data block. once the modem has read the data bytes from the data buffer, the bfree and irq bits of the status register will be set to ?1?, indicating to the c that it may write the next task and its data to the modem. note: in transmit mode the crc checksum circuit is initialized on completion of any task other than null. 4.4.2.5.17 reset - stop any current action this task takes effect immediately, and terminates any current action (task, aqbc or aqlev) the modem may be performing and sets the bfree bit of the status register to ?1?, without setting the irq bit. it should be used when v dd is applied to set the modem into a known state. note: due to delays in the internal switched capacitor filter, it will take approximately 3 bit times for any change to become apparent at the txout pin. 4.4.2.5.18 psbias - powersave bias circuit if the task bits are in this setting when b3 of the mode register is set to ?1? the device will power down the bias chain in addition to powering down those circuits described in section 4.4.4. the voltage on v bias will decay to 0v as will the level on the txout, doc1 and doc2 pins. 4.4.2.5.19 psbixt - powersave bias and xtal circuit if the task bits are in this setting when b3 of the mode register is set to ?1? the device will power down the bias chain and stop the xtal oscillator in addition to powering down those circuits described in 4.4.4. the voltage on v bias will decay to 0v as will the level on the txout, doc1 and doc2 pins. the voltage on the xtal pin will go to a logic ?1? regardless of the level at the xtal pin.
gmsk packet data modem 20 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.2.5.20 task timings the device should not write to the command register whenever psbixt and psave bits are set and for at least 2 bit times after the following: changing from powersave state to normal operation. changing the tx/rx bit. resetting or after power is applied to the device. this is to ensure that the internal operation of the device is initialized correctly for the new task. note: this only applies to the command register, the other registers may be accessed as normal. from task 2 from task 3 from task 1 t 1 t 2 task to command register data to data buffer t 3 t 4 modem tx output 12 1 2 bits to tx lowpass filter 3 ibempty bit bfree bit 3 t 2 t 2 t 3 t 3 t 4 t 4 figure 9: transmit mode timing diagram task typical time (bit-times) t 1 time from writing first task (modem in ?idle? state) to application of first transmit bit to tx low pass filter any 1 t 2 time from application of first bit of task to tx low pass filter until bfree goes to a logic ?1? (high) t7h tqb tdb tsb tsd 36 24 20 1 6 t 3 time to transmit all bits of task t7h tqb tdb tsb tsd 56 32 240 8 72 t 4 max time allowed from bfree going to a logic ?1? (high) for next task (and data) to be written to modem t7h tqb tdb tsb tsd 18 6 218 6 64
gmsk packet data modem 21 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. for task 2 for task 3 for task 1 task to command register data from data buffer modem rx input 12 1 2 bits to de-interleave circuit 3 bfree bit 3 t 5 t 7 t 5 t 5 t 6 t 7 t 7 t 6 t 6 figure 10: receive mode timing diagram task typical time (bit-times) t 3 time to receive all bits of task sfh r3h rdb rsb rsd 56 24 240 8 72 t 6 maximum time between first bit of task entering de-interleave circuit and task being written to modem sfh r3h rdb rsb rsd 14 18 218 6 64 t 7 time from last bit of task entering de-interleave circuit to bfree going to a logic ?1? (high) any 1 4.4.2.5.21 tx/rx low pass filter delay the previous task timing figures are based on the signal at the input to the tx low pass filter (in transmit mode) or the input to the de-interleave buffer (in receive mode). there is an additional delay of about 2 bit times in both transmit and receive modes due to the tx/rx low pass filter, as illustrated in figure 11. tx bit to low pass filter tx bit after tx rc network / rx bit from fm discriminator bit from rx extraction circuit bit times figure 11: low pass filter delay
gmsk packet data modem 22 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.3 control register this 8-bit write only register controls the modem?s bit rate, the response times of the receive clock extraction and signal level measurement circuits and the internal analogue filters. 76543210 control register ckdiv hi/lo dara levres pllbw 4.4.3.1 control register b7, b6: ckdiv - clock division ratio 4.4.3.2 b5: lo hi/ - xtal range selection these bits control a frequency divider driven from the clock signal present at the xtal pin, and hence determine the nominal bit rate. the table below shows how bit rates of 4000 to 38400 bits/sec may be obtained from common xtal frequencies: b5 xtal/clock frequency (mhz) 1 8.192 9.8304 4.096 (12.288/3) 4.9152 2.048 (6.144/3) 2.4576 (12.288/5) 0 4.096 (12.288/3) 4.9152 2.048 (6.144/3) 2.4576 (12.288/5) 1.024 1.2288 division ratio: b7 b6 xtal frequency data rate data rate (bits per second) 0 0 256 128 32000 38400 16000 19200 8000 9600 0 1 512 256 16000 19200 8000 9600 4000 4800 1 0 1024 512 8000 9600 4000 4800 1 1 2048 1024 4000 4800 note: device operation is not guaranteed below 4000 or above 38400 bits/sec. the values used for c3 and c4 should be suitable for the frequency of the crystal x1. as a guide; c3 = c4 = 33pf for x1 < 5mhz, and c3 = c4 = 18pf for x1 > 5mhz. 4.4.3.3 control register b4: dara - data rate and mode register b0 - hibw these bits operate in both transmit and receive modes, optimizing the modem's internal signal filtering according to the relevant bit rate. control register: b4 (dara) mode register: b0 (hibw) data rate (bits/sec) 0 0 <10k 0 1 reserved 1 0 10k ? 20k 1 1 >20k
gmsk packet data modem 23 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.3.4 control register b3, b2: levres - level measurement response time these two bits have no effect in transmit mode. in receive mode, they set the ?normal? response time of the rx signal amplitude and dc offset measuring circuits. this setting will be temporarily overridden by the automatic sequencing of an aqlev command. b3 b2 setting action 0 0 hold keep current values of amplitude and offset 0 1 peak averaging track input signal using bit peak averaging 1 0 peak detect track input signal using peak detect 1 1 lossy peak detect track input signal using lossy peak detection for mobitex systems, and most general purpose applications using the modem, these bits should normally be set to ?peak averaging? except when the c detects a receive signal fade, when ?hold? should be selected. the ?lossy peak detect? setting is intended for systems where the c cannot detect signal fades or the start of a received message, as it allows the modem to respond quickly to fresh messages and recover rapidly after a fade without c intervention - although at the cost of reduced bit error rate versus signal to noise performance. note: since the measured levels are stored on the external capacitors c6 and c7, they will decay gradually towards v bias when the ?hold? setting is chosen, the discharge time-constant being approximately 2000 bit times. more details of the level measurement system are given in section 5.3. 4.4.3.5 control register b1, b0: pllbw these two bits have no effect in transmit mode. in receive mode, they set the ?normal? bandwidth of the rx clock extraction phase locked loop circuit. this setting will be temporarily overridden by the automatic sequencing of an aqbc command. b1 b0 pll bandwidth suggested use 0 0 hold signal fades 0 1 narrow 20ppm or better xtals 1 0 medium wide tolerance xtals or long preamble acquisition 1 1 wide quick acquisition the ?hold? setting is intended for use during signal fades, otherwise the minimum bandwidth consistent with the transmit and receive modem bit rate tolerances should be chosen. the wide and medium bandwidth settings are intended for systems where the c cannot detect signal fades or the start of a received message, as they allow the modem to respond rapidly to fresh messages and recover rapidly after a fade without c intervention - although at the cost of reduced bit error rate versus signal to noise performance. note: more details of the clock extraction system are given in section 5.3. 4.4.4 mode register the contents of this 8-bit write only register control the basic operating modes of the modem: 76543210 mode register irqen scren dqen invbit tx/rx psave hixtl hibw 4.4.4.1 mode register b7: en irq - irq output enable when this bit is set to ?1?, the irq chip output pin is pulled low (to v ss ) whenever the irq bit of the status register is a ?1?.
gmsk packet data modem 24 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.4.2 mode register b6: invbit - invert bits this bit controls inversion of transmitted and received bit voltages. when set to ?1? all data is inverted in the tx and rx data paths so a transmitted '1' is a voltage below v bias at the txout pin and a received '0' is a voltage above v bias at the rxin pin. data will be inverted immediately after this bit is set to ?1?. 4.4.4.3 mode register b5: r x tx/ - tx/rx mode setting this bit to ?1? puts the modem into transmit mode, clearing it to ?0? puts the modem into receive mode. when changing from rx to tx there must be a 2-bit pause before setting a new task to allow the filter to stabilize. (see also psave bit). note: : changing between receive and transmit modes will cancel any current task 4.4.4.4 mode register b4: scren - scramble enable the scrambler only takes effect during the transmission or reception of a mobitex data block, short data block and during a tso task. setting this bit to ?1? enables scrambling, clearing it to ?0? disables scrambling. the scrambler is only operative, if enabled by this control bit, during tso, rdb, rsd, tsd or tdb, it is held in a reset state at all other times. this bit should not be changed while the modem is decoding or transmitting a mobitex data block. 4.4.4.5 mode register b3: psave - powersave when this bit is a ?1?, the modem will be in a ?powersave? mode in which the internal filters, the rx bit and clock extraction circuits and the tx o/p buffer will be disabled, and the txout pin will be connected to v bias through a high value resistance. if the psbias or psbixt bit patterns are set in the command register, the v bias and xtal/clock circuits will be powersaved in accordance with the description in section 4.4.2. setting the psave bit to ?0? restores power to all of the chip circuitry. note: the internal filters will take about 2 bit times to settle after the psave bit is taken from ?1? to ?0?. 4.4.4.6 mode register b2: dqen - data quality irq enable in receive mode, setting this bit to ?1? causes the irq bit of the status register to be set to ?1? whenever a new data quality reading is ready. (the dqrdy bit of the status register will also be set to ?1? at the same time.) in transmit mode this bit has no effect. 4.4.4.7 mode register b1: hixtl - high xtal drive this bit controls the gain of the on chip xtal driver. for 3v operation and crystals >5mhz it should be set to ?1?. at 5v, or whenever using crystals <5mhz, it should be set to ?0?. 4.4.4.8 mode register b0: hibw - high filter bandwidth this bit controls the internal filtering of the device. see control register b4 for the setting of this bit.
gmsk packet data modem 25 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.5 status register this register may be read by the c to determine the current state of the modem. 76543210 status register crcfec mo/ba irq dibovf dqrdy eop/env bfree ibempty 4.4.5.1 status register b7: irq - interrupt request this bit is set to ?1? by: the status register bfree bit going from ?0? to ?1?, unless this is caused by a reset task or by a change to the mode register psave or rx tx/ bits. or the status register ibempty bit going from ?0? to ?1?, unless this is caused by a reset task or by changing the mode register psave or rx tx/ bits. or the status register dqrdy bit going from ?0? to ?1? (if dqen = ?1' ). or the status register dibovf bit going from ?0? to ?1?. or the status register eop/env bit going from ?0? to ?1? if env or eop bits (not both) are set in the command register. or the status register eop/env bit going from ?0? to ?1? or ?1? to ?0? if both env and eop bits are set in the command register. the irq bit is cleared to ?0? immediately after a read of the status register. if the irqen bit of the mode register is ?1?, then the chip irq output will be pulled low (to v ss ) whenever the irq bit is ?1?. 4.4.5.2 status register b6: bfree - data buffer free this bit reflects the availability of the data buffer and is cleared to ?0? whenever a task other than null, reset or tso is written to the command register. in transmit mode, the bfree bit will be set to ?1? (also setting the status register irq bit to ?1?) by the modem when the modem is ready for the c to write new data to the data buffer and the next task to the command register. in receive mode, the bfree bit is set to ?1? (also setting the status register irq bit to ?1?) by the modem when it has completed a task and any data associated with that task has been placed into the data buffer. the c may then read that data and write the next task to the command register. the bfree bit is also set to ?1?, but without setting the irq bit, by a reset task or when the mode register psave or rx tx/ bits are changed. 4.4.5.3 status register b5: ibempty - interleave buffer empty in transmit mode, this bit will be set to ?1?, also setting the irq bit, when less than two bits remain in the interleave buffer. any transmit task written to the modem after this bit goes to ?1? will be too late to avoid a gap in the transmit output signal. the bit is also set to ?1? by a reset task or by a change of the mode register rx tx/ or psave bits, but in these cases the irq bit will not be set. the bit is cleared to ?0? by writing a task other than null, reset or tso to the command register. note: when the modem is in transmit mode and the interleave buffer is empty, a mid-level voltage (v bias ) will be applied to the tx low pass filter. in receive mode this bit will be ?0?.
gmsk packet data modem 26 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.5.4 status register b4: dibovf - de-interleave buffer overflow in receive mode this bit will be set to ?1? (also setting the irq bit) when a task is written to the command register too late to allow continuous reception. the bit is cleared to ?0? by reading the status register or by writing a reset task to the command register or by changing the psave or rx tx/ bits of the mode register. in transmit mode this bit will be ?0?. 4.4.5.5 status register b3: crcfec - crc or fec error in receive mode this bit will be updated at the end of a mobitex data block task, after checking the crc, and at the end of receiving frame head control bytes, after checking the fec. a ?0? indicates that the crc was received correctly or the fec did not find uncorrectable errors, a ?1? indicates that errors are present. the bit is cleared to ?0? by a reset task or by changing the psave or rx tx/ bits of the mode register. in transmit mode this bit will be ?0?. 4.4.5.6 status register b2: dqrdy - data quality reading ready in receive mode, this bit is set to ?1? whenever a data quality reading has been completed. see section 4.4.6. the bit is cleared to '0' by a read of the data quality register. immediately after a reset task, or a change in the psave or rx tx/ bits to ?0?, the dqrdy bit may be set and generate an interrupt. the value in the data quality register will not be valid in this case. 4.4.5.7 status register b1: ba mo/ - mobile or base bit sync received in receive mode this bit is updated at the end of the sfs and sfh tasks. this bit is set to ?1? whenever the 3 bits immediately preceding a detected frame sync are ?011? (received left to right), with up to any one bit in error. the bit is set to ?0? if the bit pattern is ?100?, again with up to any one bit in error. thus, if this bit is set to ?1? then the received message is likely to have originated from a mobile and if it is set to ?0? from a base station. see section 4.3. in transmit mode this bit is a logic ?0?. 4.4.5.8 status register b0: eop/env - end of packet/envelope detect this bit indicates the status of the end of packet and envelope detector circuits as indicated in the description of command register bits b5 and b4. in transmit mode this bit will be ?0?.
gmsk packet data modem 27 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.4.6 data quality register this is intended to indicate the quality of the receive signal during a mobitex data block or 30 single bytes. in receive mode, the modem measures the ?quality? of the received signal by comparing the actual received zero crossing time against an internally generated time. this value is averaged over 240 bits and at the end of the measurement the data quality register and the dqrdy bit in the status register is updated. note: an interrupt will only occur at this time if the dqen bit = ?1?. to provide synchronization with data blocks, and hence ensure the data quality register is updated in preparation to be read when the rdb task finishes, the measurement process is reset at the end of tasks sfh, sfs, rdb and r3h. the least significant 2 bits (b0 and b1) will be set to the output of the envelope and end of packet detector circuits respectively if either of the env or eop bits have been set in the command register. after a reset or if the transmit or power save modes have been set these bits will indicate the least significant bits of the quality reading. the state of the env and eop bits have no other effect on the operation of the data quality register. in transmit mode all bits of the data quality register will be ?0?. figure 12 shows how the value (0-240) read from the data quality register varies with received signal to noise ratio. 0 20 40 60 80 100 120 140 160 180 200 220 240 34 5 678910 11 12 received signal-to-noise ratio (db) data quality register reading figure 12: typical data quality reading (after 240 bits) vs. s/n, (noise in bit rate bandwidth)
gmsk packet data modem 28 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.5 crc, fec, interleaving and scrambling information: 4.5.1 crc this is a 16-bit crc code used in both the mobitex data block and short data block. in transmit it is calculated by the modem from the data block bytes using the following generator polynomial: g(x) = x 16 + x 12 + x 5 + 1 i.e. crc - ccitt x.25. this code detects all (single) error bursts of up to 16 bits in length and about 99.998% of all other error patterns. the crc register is initialized to all ?1s? and the crc is calculated octet by octet starting with the least significant bit of ?byte 0?. the crc calculated is bit-wise inverted and appended to the data bytes with the most significant bit transmitted earliest. in receive mode, a 16-bit crc code is generated from the data bytes of each mobitex data block or short data block as above and the bit-wise inverted value is compared with the received crc bytes. if a mis-match is present, then an error has been detected. 4.5.2 fec in transmit mode, during t7h, tsd and tdb, the modem generates a 4-bit forward error correction code for each coded byte. the fec is defined by the following h matrix: 7_______0 3___0 11101100 1000 h = 11010011 0100 10111010 0010 01110101 0001 generation of the fec consists of logically anding the byte to be transmitted with bits 7 to 0 of each row of the h matrix. even parity is generated for each of the 4 results and these 4 parity bits, in the positions indicated by the last 4 columns of the h matrix, form the fec code. in checking the fec, the received 12-bit word is logically anded with each row of the h matrix (earliest bit received compared with the first column). again even parity is generated for the 4 resulting words and these parity bits form a 4-bit nibble. if this nibble is all zero then no errors have been detected. other results ?point? to the bit in error or indicate that uncorrectable errors have occurred. this code can correct any single error that has occurred in each 12-bit (8 data + 4 fec) section of the message. example: if the byte to be coded is ?00101100? then the fec is derived as follows: h matrix row: 1 2 3 4 a 11101100 11010011 10111010 01110101 b 00101100 00101100 00101100 00101100 a and b 00101100 00000000 00101000 00100100 even parity: 1 0 0 0 where a is bits 7 - 0 of one row of the h matrix and b is the byte to be coded. the even parity bits apply to the result of ?a and b?. so the word formed will be: ?00101100 1000? sent left to right when the same process is carried out on these 12 bits as above, using all 12 bits of each h matrix row, the resulting 4 parity bits will be ?0000?.
gmsk packet data modem 29 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.5.3 interleaving all the bits of transmitted mobitex data blocks and short data blocks are interleaved by the modem to give protection against noise bursts and short fades. interleaving is not performed on any bits in the mobitex frame head. in the mobitex data block case, considering the 240 bits to be numbered sequentially before interleaving as 0 to 239 (?0? = bit 7 of byte 0, ?11? = bit 0 of fec for byte 0, ... , ?239? = bit 0 of fec for byte 19 - see figure 6), then they will be transmitted as shown in figure 13. the mobitex short data block is interleaved in a similar way; referring to figure 13 consider bytes 4 and 5 as the crc data and ignore bits 72 to 239 in the lower part of the diagram. i.e. the last bit to be transmitted will be ?71?. the modem performs the inverse operation (de-interleaving) in receive mode on both mobitex data blocks and short data blocks. 0 12 24 36 48 60 72 84 96 108 120 132 144 156 168 180 192 204 216 228 7 input data interleaved output to low pass filter data block 1 13 25 37 49 61 73 85 97 109 121 133 145 157 169 181 193 205 217 229 6 2 14 26 38 50 62 74 86 98 110 122 134 146 158 170 182 194 206 218 230 5 3 15 27 39 51 63 75 87 99 111 123 135 147 159 171 183 195 207 219 231 4 4 16 28 40 52 64 76 88 100 112 124 136 148 160 172 184 196 208 220 232 3 5 17 29 41 53 65 77 89 101 113 125 137 149 161 173 185 197 209 221 233 2 6 18 30 42 54 66 78 90 102 114 126 138 150 162 174 186 198 210 222 234 1 7 19 31 43 55 67 79 91 103 115 127 139 151 163 175 187 199 211 223 235 0 8 20 32 44 56 68 80 92 104 116 128 140 152 164 176 188 200 212 224 236 3 9 21 33 45 57 69 81 93 105 117 129 141 153 165 177 189 201 213 225 237 2 10 22 34 46 58 70 82 94 106 118 130 142 154 166 178 190 202 214 226 238 0 1 11 23 35 47 59 71 83 95 107 119 131 143 155 167 179 191 203 215 227 239 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 crc crc loaded first loaded last 0 12 24 36 48 60 72 84 96 108 120 132 144 156 168 180 192 204 216 228 1 13 25 37 49 61 73 85 97 109 121 133 145 157 169 181 193 205 217 229 2 14 26 38 50 62 74 86 98 110 122 134 146 158 170 182 194 206 218 230 3 15 27 39 51 63 75 87 99 111 123 135 147 159 171 183 195 207 219 231 4 16 28 40 52 64 76 88 100 112 124 136 148 160 172 184 196 208 220 232 5 17 29 41 53 65 77 89 101 113 125 137 149 161 173 185 197 209 221 233 6 18 30 42 54 66 78 90 102 114 126 138 150 162 174 186 198 210 222 234 7 19 31 43 55 67 79 91 103 115 127 139 151 163 175 187 199 211 223 235 8 20 32 44 56 68 80 92 104 116 128 140 152 164 176 188 200 212 224 236 9 21 33 45 57 69 81 93 105 117 129 141 153 165 177 189 201 213 225 237 10 22 34 46 58 70 82 94 106 118 130 142 154 166 178 190 202 214 226 238 11 23 35 47 59 71 83 95 107 119 131 143 155 167 179 191 203 215 227 239 input data resulting fec first out last out byte figure 13: interleaving - input/output
gmsk packet data modem 30 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 4.5.4 scrambling all formatted bits of both mobitex data blocks and short data blocks are passed through a 9-bit scrambler. this scrambler is initialized at the beginning of the first data block in every frame. the 511-bit sequence is generated with a 9-bit shift register with the output of the 5th and 9th stages xor?ed and fed back to the input of the first stage. the scrambler is disabled during all other tasks, apart for tso. 5. application notes 5.1 transmit frame example if the device is required to send a mobitex frame the following control signals and data should be issued to the modem, assuming the device is not starting from a powersave state, rx tx/ is set to ?1? and that the relevant control bits have been set as required after power was applied to the device: 1. 6 bytes forming the frame head are loaded into the data buffer, followed by a 2-bit pause to let the filter stabilize, followed by setting t7h task. 2. device interrupts host c with irq when the 6th byte is read from the data buffer. 3. status register is read and 18 bytes are loaded, followed by setting tdb task. 4. device interrupts host c with irq when 18th byte is read from the data buffer. 5. status register is read, host may load data and set next task as required: goto ?1? if the last data block for this frame has been transmitted and another frame is to be immediately transmitted goto ?3? if another data block in this frame is to be transmitted goto ?6? if no more data is to be immediately sent 6. 1 byte representing the ?hang byte? is loaded into the data buffer, followed by setting the tsb task. if the ?hang byte? has been transmitted and no more data is to be sent then a new task need not be written and the c can wait for the ibempty interrupt when, after a few bits to allow for the tx filter delay, it can shut down the tx rf circuits. a top level flowchart of the transmit process is shown in figure 14. hang byte the filtering required to reduce the transmitted bandwidth causes energy from each bit of information to be smeared across 3 bit times. to ensure that the last bit transmitted is received correctly it is necessary to add an 8-bit ?hang byte? to the end of each message. thus the tasks required to transmit an isolated mobitex frame are: t7h + (n x tdb) + tsb when receiving this data, the extra byte can be ignored as its only function is to ensure integrity of the last bit and not to carry any information itself. it is suggested that a ?00110011? or ?11001100? pattern is used for this ?hang byte?.
gmsk packet data modem 31 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. start write task = 'reset' to command register write 6 bytes of frame head to data buffer write 18 bytes of data to data buffer set c data block counter to length of message wait 2-bit times for lowpass filter to settle write task = tdb to command register write ckdiv, hi/ , and dara values to control register lo write task = 't7h' to command register wait for line to go low then execute tx i.s.r. irq write irqen = '1' scren = '1', tx/ = '1' to mode register rx wait for line to go low then execute tx i.s.r. irq decrement c data block counter read status register data block counter = '0'? data block counter = '0'? bfree = '1'? write 'hang byte' to data buffer write task = 'tsb' to command register read status register finish tx interrupt service routine (i.s.r.) irq bit = '1'? service other interrupts fault detected: abort transmission fault detected: abort transmission ibempty = '1'? bfree = '1'? no ye s no ye s no ye s no ye s ye s no no ye s figure 14: transmit process
gmsk packet data modem 32 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 5.2 receive frame example if the device is required to decode a mobitex frame the following control signals should be issued to the modem, assuming the device is initially not in powersave, pllbw, levres, scren are set as required, rx tx/ bit is set to ?0?, the frame sync bytes have not been set and the carrier has been detected, or a frame head is imminently expected: 1. 2 frame sync bytes are loaded. 2. 2 bits after the carrier has been detected, a lfsb task is loaded, along with setting the aqlev and aqbc bits, to initiate the level acquisition and bit clock extraction sequences. 3. device interrupts host c with irq when 2nd byte is read from data buffer. 4. status register is read, 12 bits later task is set to sfh to search for a mobitex frame head. 5. device will interrupt host c with irq when valid frame sync is detected and header bytes decoded. 6. host c reads status register, checks ba mo/ and crcfec bit and reads out 2 frame head control bytes. 7. host c sets the task to rdb to receive a mobitex data block. 8. device will interrupt host c with irq when the data block has been received and the crc has been calculated. 9. host c reads status register, checks crc validity and reads 18 data block bytes. the data quality register can also be read to obtain the received s/n level. 10. host c sets task if more information is expected: goto ?4? if last data block and another frame head imminently expected. goto ?7? if another mobitex data block expected. if the last data block has been decoded and no more information is expected then the task bits need not be set as the device will automatically select the idle state. a top level flowchart of the receive process is shown in figure 15.
gmsk packet data modem 33 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. start a b write task = reset to command register write pllbw, levres, dara, and ckdiv values to control register data carrier detected write 2 frame sync bytes to data buffer read mo/ba and crcfec bits from status register read 2 byte frame head from data buffer write task = lfsb, aqlev = '1', aqbc = '1' to command register, write task = sfh to command register wait 2 bit periods wait 12 bit periods log "nth block in error" in c finish ye s ye s ye s no no no crcfec = '1' ? c expect new frame head c expect mobitex data block? read 18 bytes of data from data buffer a b write task = rdb to command register wait for irq line to go low then execute rx i.s.r. wait for irq line to go low then execute rx i.s.r. wait for irq line to go low then execute rx i.s.r. write irqen = '1', scren = '1', txrx = '1' to mode register ye s ye s no read status register dibovf = '1' ? bfree = '1' ? fault detected: abort reception fault detected: abort reception service other interrupts rx interrupt service routine (i.s.r.) irq bit = '1' ? no no ye s figure 15: receive process
gmsk packet data modem 34 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 5.3 clock extraction and level measurement systems the modem needs to make accurate measurements of the received signal amplitude, dc offset and bit timing to achieve reasonable error rates. accurate measurements, especially in the presence of noise, are best made by averaging over a relatively long time. however, in most cases the modem will be used to receive isolated messages from a distant transmitter that is only turned on for a very short time before the message starts. also, the received baseband signal out of the radio's frequency discriminator will have a dc offset due to small differences between the receiver and transmitter reference oscillators and hence their ?carrier? frequencies. to cater for this situation, aqbc and aqlev (acquire bit clock and level) commands are provided which, when triggered, causes the modem to follow an automatic sequence designed to perform these measurements as quickly as possible. the aqlev sequence always starts with a measurement of the average signal voltage over a period of 1 bit time. the sequence continues by measuring the positive going and negative going peaks of the signal. the attack and decay times used in this ?lossy peak detect? mode are such that a sufficiently accurate measurement can be made within 16 bits of a ?1100 ...? pattern (i.e. the bit sync sequence) to allow the bit clock extraction circuits to operate. if sfh or sfs is set within 28 bit times of aqlev the device will switch to the residual setting when frame sync is found. if a sfh or sfs task is not set then the residual setting will be active 30 bits after aqlev was set. the residual setting is that programmed in the levres bits and is either ?lossy peak detect?, ?peak detect?, ?peak averaging? or ?hold?. note: for normal operation the levres bits would only be set to 'hold' for the duration of a fade. if sfh or sfs is set within 14 bit times of aqbc the device will switch to the medium setting when frame sync is found. if a sfh or sfs task is not set then the medium setting will be active 16 bits after aqbc was set. the pllbw will change to the residual setting 30 bits later. the complete aqbc and aqlev sequence is illustrated below, for the situation where the c can detect the received carrier so that it knows when to issue the aqbc and aqlev commands. note: due to the delay through the rx low pass filter, the aqbc and aqlev sequences should not be started until about 2 bit times after the received carrier has been detected at the discriminator output. see figure 16. in a system where the host c is not able to detect the received carrier, the aqbc and aqlev sequences may be started at any time - possibly when no carrier is being received. however, in this case the clock and level acquisition will take longer since the circuits will have to recover from the change from a large amplitude noise signal at the output of the frequency discriminator to the wanted signal, probably with a dc offset. in this type of system, the time between the turn-on of the transmitter and the start of the frame sync pattern should be extended - preferably by extending the bit sync sequence to 32 or even 48 bits. note: the clock extraction circuits work by detecting the timing of edges, i.e. a change from ?0? to ?1? or ?1? to ?0?. they will eventually fail if ?1? or ?0? is transmitted continuously. similarly, the level measuring circuits require ?00?and ?11? bit pairs to be received at reasonably frequent intervals. aqlev sequence sfh or sfs is set up to 28 bits after aqlev; frame sync is being searched for: 1 bit of clamp. lossy peak detect until frame sync is detected. residual setting. sfh or sfs is not set; frame sync is not being searched for: 1 bit of clamp. 30 bits of lossy peak detect. residual setting. aqbc sequence sfh or sfs is set up to 14 bits after aqbc; frame sync is being searched for: ?wide? setting until frame sync detected. 30 bits of ?medium? setting. residual setting. sfh or sfs is not set; frame sync is not being searched for: 16 bits of ?wide? setting. 30 bits of ?medium? setting. residual setting.
gmsk packet data modem 35 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. rx signal from fm discriminator to modem noise frame sync rest of frame set aqbc and aqlev bits to start acquisition sequences level measurement and clock extraction circuits increasing accuracy and lengthening response times 2-bit delay (min.) bit sync reset figure 16: bit clock and level acquisition example
gmsk packet data modem 36 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 5.4 ac coupling for a practical circuit, ac coupling from the modem?s transmit output to the frequency modulator and between the receiver?s frequency discriminator and the receive input of the modem may be desired. there are, however, two problems. 1. ac coupling of the signal degrades the bit error rate performance of the modem. see figure 17. signal-to-noise ratio (db) (noise in 8khz bandwidth) bit-error-rate 10 -2 4 5 6 7 8910 11 12 13 tx and rx dc coupled tx 5hz, rx dc coupled tx 5hz, rx 10hz tx 5hz, rx 30hz tx 5hz, rx 100hz 10 -1 10 -3 10 -4 10 -5 figure 17: typical bit error rates (at 8kbits/sec, without fec, for different degrees of ac coupling) 2. any ac coupling at the receive input will transform any step in the voltage at the discriminator output to a slowly decaying pulse which can confuse the modem?s level measuring circuits. as illustrated below, the time for this step to decay to 37% of its original value is ?rc? where rc = 1/( 2 x x the 3db cut-off frequency of the rc network ) and is 8ms - or 64 bit times at 8kbits/sec for a 20hz network. see figure 18. 37% t = rc 100% step input to rc circuit output of rc circuit figure 18: decay time - ac coupling for these reasons the maximum 3db cut-off frequencies would seem to be around 5hz in the tx path and 20hz in the rx path at 8kbits/sec.
gmsk packet data modem 37 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 5.5 radio performance the maximum data rate that can be transmitted over a radio channel using this modem depends on: - rf channel spacing. - allowable adjacent channel interference. - bit rate. - peak carrier deviation (modulation index). - tx and rx reference oscillator accuracies. - modulator and demodulator linearity. - receiver if filter frequency and phase characteristics. - use of error correction techniques. - acceptable error rate. as a guide, 8000 bits/sec can be achieved (subject to local regulatory requirements) over a system with 12.5khz channel spacing if the transmitter frequency deviation is set to 2khz peak for a repetitive ?1100?? pattern and the maximum difference between transmitter and receiver ?carrier? frequencies is less than 1500hz. the modulation scheme employed by this modem is designed to achieve high data throughput by exploiting as much as possible of the rf channel bandwidth. this does, however, place constraints on the performance of the radio. in particular, attention must be paid to: - linearity, frequency and phase response of the tx frequency modulator. - the bandwidth and phase response of the receiver?s if filters. - accuracy of the tx and rx reference oscillators, as any difference will shift the received signal towards the skirts of the if filter response and cause a dc offset at the discriminator output. viewing the received signal eye pattern, using the output of the frequency discriminator, gives a good indication of the overall transmitter/receiver performance. rx circuits tx circuits cs rd wr irq txout signal and dc level adjustment signal level adjustment rxin rxampout rx frequency discriminator c tx frequency modulator dc level adjustment CMX909B gmsk modem d0-d7 a0-a1 cs rd wr irq a0-a1 d0-d7 figure 19: typical system installation
gmsk packet data modem 38 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 6. performance specification 6.1 electrical performance 6.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (v dd - v ss ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current into or out of v dd and v ss pins -30 +30 ma current into or out of any other pin -20 +20 ma e2 package total allowable power dissipation at t amb = 25c - 300 mw derating above 25c - 5 mw/c above 25c storage temperature -55 +125 c operating temperature -40 +85 c d5 package total allowable power dissipation at t amb = 25c - 550 mw derating above 25c - 9 mw/c above 25c storage temperature -55 +125 c operating temperature -40 +85 c p4 package total allowable power dissipation at t amb = 25c - 800 mw derating above 25c - 13 mw/c above 25c storage temperature -55 +125 c operating temperature -40 +85 c 6.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max. units supply (v dd - v ss ) 2.7 5.5 v operating temperature -40 +85 c xtal frequency 1.0 10.0 mhz
gmsk packet data modem 39 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. 6.1.3 operating characteristics for the following conditions unless otherwise specified: xtal frequency = 4.096mhz, bit rate = 8k bits/sec, noise bandwidth = bit rate, v dd = 3.0v to 5.5v, t amb = -40c to +85c. notes min. typ. max. units dc parameters i dd (running, v dd = 3.0v) 1 - 2.0 tba ma i dd (running, v dd = 5.0v) 1 - 2.9 tba ma i dd (powersave, v dd = 3.0v) 1 - 0.4 tba ma i dd (powersave, v dd = 5.0v) 1 0.9 tba ma i dd (powersave + no bias) 1 - tba - a i dd (powersave + no bias or xtal) 1 - tba - a ac parameters tx output txout impedance (not powersaved) 2 - 1.0 2.5 k ? txout impedance (powersaved) 2 - 300 - k ? signal level 3 0.9 1.0 1.1 v pk-pk tx data delay 4 - 4 6 bits txout dc offset (with respect to tx mode with data) 3 - - mv (in tx mode, no data) - tba - (in rx mode) - tba - mv (in powersave, bias enabled) - tba - mv rx input rxin impedance (at 100hz) 10.0 - - m ? rxin amp voltage gain (i/p = 1mv rms at 100hz) - 500 - v/v input signal level 5 0.7 1.0 1.3 v pk-pk rx data delay 6 - 3.5 - bits xtal/clock input ?high? pulse width 7 40 - - ns ?low? pulse width 7 40 - - ns input impedance (at 100hz) 10.0 - - m ? gain (input = 1mv rms at 100hz) 20 - - db c interface input logic ?1? level 8, 9 70% - - v dd input logic ?0? level 8, 9 - - 30% v dd input leakage current (v in = 0 to v dd ) 8, 9 5.0 - +5.0 a input capacitance 8, 9 - 10.0 - pf output logic ?1? level (l oh = 120a) 9 90% - - v dd output logic ?0? level (l ol = 360a) 9,10 - - 10% v dd ?off? state leakage current (v out = v dd ) 10 - - 10 a
gmsk packet data modem 40 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. notes: 1. not including any current drawn from the modem pins by external circuitry other than r3, x1, c3 and c4. 2. small signal impedance, at v dd = 5.0v and t amb = 25c. 3. for ??1111000011110000...? bit sequence, at v dd = 5.0v and t amb = 25c (output level is proportional to v dd ). 4. measured between issuing first task after idle and the center of the first bit at txout (see figure 7). 5. for optimum performance, measured at rxfb pin, for a ?...11110000...? bit sequence, at v dd = 5.0v and t amb = 25c. 6. measured between center of last bit of an rx single byte or frame sync at rxin and an irq interrupt to the host c. 7. timing for an external input to the xtal/clock pin. 8. wr , rd , cs , a0 and a1 pins. 9. d0 - d7 pins. 10. irq pin. 6.1.4 timing diagrams for the following conditions unless otherwise specified: xtal frequency = 4.096mhz, v dd = 3.0v to 5.5v, t amb = -40c to +85c. c parallel interface timings (ref. figure 20) notes min. typ. max. units t acsl address valid to cs low time 0 - - ns t ah address hold time 0 - - ns t csh cs hold time 0 - - ns t cshi cs high time 2 6 - - clock cycles t csrwl cs to wr or rd low time 0 - - ns t dhr read data hold time 0 - - ns t dhw write data hold time 0 - - ns t dsw write data setup time 90 - - ns t rhcsl rd high to cs low time (write) 0 - - ns t racl read access time from cs low 2 - - 175 ns t rarl read access time from rd low 2 - - 145 ns t rl rd low time 200 - - ns t rx rd high to d0-d7 3-state time - - 50 ns t whcsl wr high to cs low time (read) 0 - - ns t wl wr low time 200 - - ns notes: 1. with 30pf max to v ss on d0 - d7 pins. 2. xtal/clock cycles at the xtal/clock pin.
gmsk packet data modem 41 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. data d0 to d7 (1 byte) read cycle (data from modem) address valid data d0 to d7 (1 byte) t rl t dhr t rx data va l i d data valid write cycle (data to modem) t csrwl t rhcsl t dsw t dhw t whcsl t rarl t racl address a0 a1 , t ah t acsl t csrwl t wl t cshi t csh t ah t acsl t cshi t csh address valid cs wr rd address a0 a1 , cs wr rd figure 20: c parallel interface timings
gmsk packet data modem 42 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. signal-to-noise ratio (db) error rate 10 -6 10 -3 10 -2 10 -1 10 4 56 78 9 10 11 12 block error rate (with fec) bit error rate (no fec) note: a block is deemed to be "in error" if the crc fails 10 -4 10 -5 figure 21: typical bit error rate (noise in bit rate bandwidth) 6.2 packaging figure 22: 24-pin tssop (e2) mechanical outline: order as part no. CMX909Be2
gmsk packet data modem 43 of 43 CMX909B advance information 2001 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480226.001 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective comp anies. figure 23: 24-pin ssop (d5) mechanical outline: order as part no. CMX909Bd5 figure 24: 24-pin pdip (p4) mechanical outline: order as part no. CMX909Bp4

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